This invention relates to nonvolatile memory arrays, such as electrically-erasable, electrically-programmable, read-only-memories (EEPROMs) of the single-transistor type and to eliminating errors that occur in reading EEPROM cell arrays having over-erased cells.
In particular, the invention relates to avoiding or eliminating read errors resulting from over-erasing the floating-gate conductors of nonvolatile memory arrays. An EEPROM cell is over-erased when an excessive number of electrons is removed from its floating gate during an erasing operation. The source-drain path of an over-erased EEPROM cell is conductive with the control gate and the source or drain at the same electric potential.
EEPROM arrays include floating-gate memory cells arranged in rows and columns. The floating gate of a programmed memory cell is charged with electrons, and the electrons in turn render the source-drain path under the charged floating gate nonconductive when a chosen wordline select voltage is applied to the control gate. The nonconductive state is read as a "zero" bit. The floating gate of a non-programmed cell is positively charged, is neutrally charged, or is slightly negatively charged, such that the source-drain path under the non-programmed floating gate is conductive when the same chosen wordline select voltage is applied to the control gate. The conductive state is read as a "one" bit.
Each column and row of an EEPROM array may contain thousands of cells. The sources of each cell in a column are connected to a bitline (source-column line). The drains of each cell in a column are connected to a separate bitline (drain-column line). The control gates of each cell in a row are connected to a wordline. Prior to first programming, or perhaps after erasure by ultraviolet light, the source-drain paths of the cells begin to conduct at a uniform control-gate threshold voltage Vt because the floating gates are neutrally charged (having neither an excess of electrons nor a deficiency of electrons). The initial uniform threshold voltage Vt may be, for example, +2.5 volts between control gate and source. The initial uniform threshold voltage Vt may be adjusted by appropriately doping the channel regions of the cells during manufacture.
After programming, the source-drain paths of the programmed cells have control-gate threshold voltages Vt distributed over a range between +6 volts to +9 volts, for example. The distribution of threshold voltages Vt among individual cells is caused by processing variations, including variations in the tunnel oxide thicknesses, the areas of tunneling regions and in the coupling ratios of the control-gate voltages to the floating gates, as well as variations in the programming voltages applied to individual cells.
After electrical erasure of the cells, the threshold voltages Vt of the erased cells may, for example, be distributed
over a range from perhaps +0.5 to 2.5 volts with the majority of the cells having erased threshold voltages Vt near +1.5 volts, the range depending on the localized variations in the tunnel oxide thickness, the areas of tunneling regions, the capacitive coupling ratios between wordlines and floating gates, and the strengths of the erasing pulses. Using a lower-strength erasing pulses, the range may be from perhaps +1.5 to +3.5 volts with the majority of the cells having erased threshold voltages Vt near 2.5 volts. With higher-strength erasing pulses applied, the distribution may range from perhaps -0.5 to +1.5 volts with the majority of cells having erased threshold voltages Vt near +0.5 volt. Cells with erased threshold voltages Vt less than that set during the manufacturing process have deficiencies of electrons (or have net positive charges) on the floating gates. The excess of positive charges on the floating gates causes the channel regions under such gates to be enhanced with electrons.
In general, the extent of channel doping, the programming pulse strength, the erasing pulse strength and other factors are chosen such that the source-drain path of a cell will either be conductive or non-conductive when applying a chosen wordline select voltage to the control gate. The select voltage must have a value somewhere between the highest erased-threshold-voltage value of erased cells and the lowest programmed-threshold-voltage value of the programmed cells. In many memory arrays, the channel doping, programming/erasing voltages and other factors are chosen such that the wordline select voltage is equal to the available chip supply voltage Vcc, which may be +5 volts. With +5 volt applied to the control gate, the source-drain paths of all of the properly erased cells are conductive only if those cells have threshold voltages Vt below the +5 volt select voltage. Similarly, the source-drain paths of all of the properly programmed cells are non-conductive only if those cells have threshold voltages Vt greater than the +5 volt select voltage. To guarantee that the correct state of a cell is sensed with a reasonable speed, even with a noisy chip supply voltage Vcc and with other typical fluctuations in drain bitline voltage, all of the threshold voltages Vt of erased cells should be considerably less than +5 volts, perhaps less than +3.5 volts, and all of the threshold voltages Vt of programmed cells should be considerably greater than +5 volts, perhaps greater than +6.0 volts.
One of the problems associated with EEPROMs of the type without split gates is the difficulty of reading memory arrays after some of the cells have been over-erased, becoming depletion-mode devices. Because the channel regions of the over-erased cells are in connected in parallel with all of the source-drain paths of other cells in a column, inaccuracies during reading operation may occur where the stored data in those columns is short-circuited by the over-erased cells. At least some of the over-erased cells may be conductive because the excessive positive charge on the floating gates causes the channel regions to invert from P-type to N-type.
The problems of over-erasure may be avoided by constructing cells with pass gates, or split gates, in which the channel between source and drain comprises two series sections, one section having the control gate separated from the channel region by the gate dielectric, the second region having the floating gate separated from the channel region by the gate dielectric. However, such memory cells require more area on a silicon chip than do cells without split gates.
The problem of over-erasure may also be minimized by performing multiple erasing operations, each operation increasing the erasing energy applied to the floating gate. Between each operation, the threshold voltages Vt of all of the cells may be checked to see that a given maximum threshold voltage Vt is not exceeded. However, that procedure does not provide correction for any cells that may be over-erased.
Alternatively, a similar procedure may be used to check between increased-energy erasing pulses to determine that the minimum erased threshold voltage Vt does not become less than some value greater than zero. However, this does not always guarantee that the highest erased threshold voltage Vt is low enough and, therefore, some of the cells may remain programmed. The highest erased threshold voltage Vt will determine the speed at which the memory will operate.
The circuit and method of U.S. Patent Application Ser. No. 07/367,597, filed June 19, 1989, and also assigned to Texas Instruments Incorporated, relate to normal erasure of the cells of a memory array followed by application of relatively low-energy pre-conditioning pulses to the cells prior to reprogramming the array. The low-energy pulses may tend to program and/or erase the cells, depending on the which is needed to distribute the threshold voltages between 0 volts and the select wordline voltage. The circuit and method of U.S. Patent Application Ser. No. 07/509,532, filed Apr. 16, 1990 and also assigned to Texas Instruments Incorporated, relate to erasure of the cells of a memory array through alternate application of relatively high-energy programming and erasing pulses, followed by alternate application of alternate programming and erasing pulses with decreasing energy levels.
In the alternative, the negative-voltage method of U.S. Patent Application Ser. No. 07/437,553, filed Nov. 17, 1989 and also assigned to Texas Instruments Incorporated may be used to eliminate the adverse effects of over-erasure of memory cells. However, use of a negative voltage applied to wordlines requires special driver circuitry.
As yet another alternative for eliminating over-erasure errors, the channel regions of the EEPROM cells may have increased doping and the read voltages may be increased as described in U.S. Patent Application Ser. No. 07/437,553, filed Nov. 16, 1989 and also assigned to Texas Instruments Incorporated.
There is a need for an alternative circuit and procedure that permit an EEPROM array to be read without the need for special driver circuitry, while at the same time permitting minimum-size memory cells without split gates. The circuit and procedure should eliminate errors caused by cells with excessively high or low threshold voltages Vt caused by conventional erasing methods.